Designing and architecting digital IP and subsystems. Making sure the IP under test gets fully verified by the verification engineer.

Designing and architecting the SoC level integrating all IP and subsystems. Aiding in verifying the SoC functionality with top-level tests. Deep understanding of the SW-HW system.

Assisting and/or performing all front-end design tasks: design, verification, DFT, synthesis, STA and formal equivalence checking.

At least 10 years of experience in ASIC Design.

Demonstrate ability to design from scratch complex digital modules, preferably in the area of hw accelerators, Computer Vision, DSP or Neural Netwoks. Power aware design and understanding of power domains.

Experience in architecting complex SOC subsystems or even entire SOCs.

Strong documentation skills.

Demonstrate the ability to work within a team with minimum supervision.

Design or integration of RISC/DSP processors and their ecosystem.

Strong verification skills with impeccable reuse and best practices.

Experience with various fast&slow communication protocols (SPI, I2C, UART, …) and on-chip bus protocols (AMBA, OBI, …).

Test methodologies (using JTAG, scan, memory BIST).

EDA tool flows and scripting (eg: in Python).

Version control (git) and CI/CD (github, gitlab, Jenkins, …).

(Embedded) C and/or C++ and/or System C.

Synthesis, timing analysis and timing closure.

Chip bring-up, silicon and system debug.

The perfect cultural fit is someone who is fearless, curious and ambitious. But mostly team oriented. 

A dynamic working environment around a fearless engineering culture,

Ambitious teams with the freedom to innovate,

A Flexible working environment (work from home policy, flexible working hours, advantageous holidays scheme ..),

An inclusive company culture which embraces communication, diversity and support around holistic and personal development.