Leading and execute electrical analysis at block and top levels, including ESD, EM, IR;

Driving verification closure across ESD, EMIR, and IO pad electrical integrity;

Defining and implementing ESD methodology across all Innatera silicon;

Designing and validating ESD protection devices and circuits, including test structures for Si characterization;

Collaborate with foundry partners on ESD design rule development and ESD library and LUP rule integration;

Support internal teams with PDK installation, updates, and IP-related support;

Partner with CAD and tool vendors to enhance and validate new flows and electrical analysis methodologies;

Support technology characterization efforts for design enablement and scaling.

BS + 6 or MS + 4 years of relevant industry experience;

Deep understanding of transistor behavior and ESD phenomena (HBM, CDM, MM models);

Experience designing ESD circuits and validating ESD robustness;

Familiarity with ESD check tools like Pathfinder or PERC;

Hands-on experience with EMIR tools (e.g., Cadence Totem, Voltus);

Experience with Virtuoso, Calibre, and related physical design tools;

Good understanding of system-level power distribution networks (PDN) and power integrity concepts;

Experience characterizing ESD/LUP in silicon and translating that into design rules;

Working knowledge of scripting (e.g., Python, TCL, Perl) and Linux environments;

Previous involvement with PDK maintenance or IP support is a strong plus.

Self-starter mindset;

Strong collaboration, problem-solving, and communication skills.